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Parametric Probes
Parametric Tests Accelerate Learning Cycles
During new technology development, it is desirable to ascertain the effects of device parameters such as doping, width, length, thickness, etcetera on device performance. Thus, variant device designs are implemented on a reticle and manufactured as a test chip. Traditional test pads that connect to a device-under-test (DUT) are large (~60 µm) resulting in smaller number of DUTs per test chip. Thus, a test chip might have inadequate number of DUTs to accurately, reliably, and timely model device performance, resulting in new test chip development and manufacturing, with a negative impact on learning cycles, manufacturing costs, and time-to-market.
Fine pitch parametric tests reduce learning cycles and manufacturing costs
Fine Pitch Parametric Probes
Our parametric probes have dramatically reduced probe width, pitch, and tip surface area, enabling more DUTs per test chip. For advanced node multi-purpose-wafers (MPW) where silicon real estate comes at a premium, use of 10X smaller test pads could result in smaller dice at significantly lower cost per die.
Combined with the HITS-300 and SAKYIWA NanoProber, our fine pitch parametric probes allow for electrical tests of macros and test vehicles on 300 mm, 200 mm, 100 mm, and pieces at the micro and nanoscale. In addition to our current standard 1×25 parametric probes (10 µm pitch), we design and manufacture a portfolio of fine pitch parametric probes with a full range of probe spacing, tip materials, and radii. Please contact us for more information about our custom and nanoscale parametric probes.
Reduce die size and cost with fine pitch pads
Applications
- Parametric IV
- Transmission line measurements (TLM)
- Sheet resistance
- 4-wire Kelvin resistance
Specifications
- Number of tips: 25
- Arrangement: Inline
- Probe width: 5 µm ±1 µm
- Pitch: 10 µm
- Probe-to-probe leakage current: ~500 pA @ 5 V
- Current carrying capacity: 100 mA
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