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Heterogeneous Integration Test System (HITS™)
ONE HITS – Unified Test System
As the semiconductor industry adopts 2.5D and 3D heterogeneous integration to extend Moore’s Law, chiplets have become the building blocks of next-generation performance. By integrating miniature integrated circuits with specialized functions, chiplets offer optimized power, lower manufacturing costs, and unparalleled scalability. However, this complexity demands perfection; systematic or random faults during manufacturing can persist across batches, devastating yields and inflating packaging costs. Ensuring a “Known-Good Die” is no longer optional—it is a baseline requirement.
The Heterogeneous Integration Test System (HITS™) is our premier semi-automatic solution for chiplet, advanced package, and thin-film characterization. By leveraging Xallent’s portfolio of fine-pitch probe cards and proprietary automation software, HITS™ delivers early actionable insights that accelerate R&D and secure high-volume manufacturing. Designed for versatility, HITS™ supports full-wafer testing for 300 mm, 200 mm, and 100 mm formats, as well as individual die and small-form-factor pieces.
Reduce capital expenditure with a single tool for inspection, metrology, and probing
Nanoscale resolution of the HITS enables the probing of chiplets with fine pitch microbumps and hybrid bond pads
Leveraging powerful computer vision algorithms to guide the probing sequence, HITS™ reduces operational overhead by targeting only viable devices. Both probe card longevity and measurement precision are significantly enhanced through proactive defect avoidance, which prevents fine-pitch tips from making contact with surface particles or localized contaminants. To support these capabilities, we offer a versatile portfolio of fine-pitch solutions—including 4-point, parametric, and custom probes—engineered for the industry’s most demanding applications.
Applications
Kelvin Resistance Measurements: Execute high-fidelity Kelvin and sheet resistance measurements on microbumps, copper pillars, and hybrid bond pads with sub-micron precision.
Parametric Testing: Implement robust process control monitoring (PCM) across both chiplet manufacturing and advanced assembly workflows.
Functional Validation: Validate chiplet functionality both prior to singulation and after final assembly to ensure Known-Good Die (KGD) status.
Defect Inspection: Utilize advanced computer vision algorithms to identify and isolate faulty hybrid bond pads and microbumps before they impact yield.
Specifications
- Supports up to 300 mm wafers and pieces
- Vision system with sub-1 µm resolution
- Accepts fine pitch probe cards
- Autofocus and light intensity adjustment
- Utilizes control & feedback algorithms to bring probe tips into contact with wafer
- Leverages optical inspection data to guide electrical tests
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